HEAL-WEAR: an Ultra-Low Power Heterogeneous System for Bio-Signal Analysis

Personalized healthcare devices enable low-cost, unobtrusive and long-term acquisition of clinically-relevant biosignals. These appliances, termed Wireless Body Sensor Nodes (WBSNs), are fostering a revolution in health monitoring for patients affected by chronic ailments. Nowadays, WBSNs often embed complex digital processing routines, which must be performed within an extremely tight energy budget. Addressing this challenge, in this paper we introduce a novel computing architecture devoted to the ultra-low power analysis of biosignals. Its heterogeneous structure comprises multiple processors interfaced with a shared acceleration resource, implemented as a Coarse Grained Reconfigurable Array (CGRA). The CGRA mesh effectively supports the execution of the intensive loops that characterize bio-signal analysis applications, while requiring a low reconfiguration overhead. Moreover, both the processors and the reconfigurable fabric feature Single-Instruction / Multiple- Data (SIMD) execution modes, which increase efficiency when multiple data streams are concurrently processed. The run-time behavior on the system is orchestrated by a light-weight hardware mechanism, which concurrently synchronizes processors for SIMD execution and regulates access to the reconfigurable accelerator. By jointly leveraging run-time reconfiguration and SIMD execution, the illustrated heterogeneous system achieves, when executing complex bio-signal analysis applications, speedups of up to 11.3x on the considered kernels and up to 37.2% overall energy savings, with respect to an ultra-low power multicore platform which does not feature CGRA acceleration

A Multi-Core Reconfigurable Architecture for Ultra-Low Power Bio-Signal Analysis

This paper introduces a novel computing architecture devoted to the ultra-low power analysis of multiple bio-signals. Its structure comprises several processors interfaced with a shared acceleration resource, implemented as a Coarse Grained Reconfigurable Array (CGRA). The CGRA supports the efficient execution of the computationally intensive kernels present in this application domain, while requiring a low reconfiguration overhead. The run-time behavior of the resulting heterogeneous system is orchestrated by a light-weight hardware mechanism, which concurrently synchronizes processors and regulates access to the reconfigurable accelerator. The architecture achieves speed-ups of up to 11x on different bio-signal processing kernels and system-level energy savings of up to 18.6%, with respect to a multi-core platform, which does not feature CGRA acceleration

An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery

The energy efficiency of digital architectures is tightly linked to the voltage level (Vdd) at which they operate. Aggressive voltage scaling is therefore mandatory when ultra-low power processing is required. Nonetheless, the lowest admissible Vdd is oen bounded by reliability concerns, especially since static and dynamic non-idealities are exacerbated in the near-threshold region, imposing costly guard-bands to guarantee correctness under worst-case conditions. A striking alternative, explored in this paper, waives the requirement for unconditional correctness, undergoing more relaxed constraints. First, aer a run-time failure, processing correctly resumes at a later point in time. Second, failures induce a limited Quality-of-Service (QoS) degradation. We focus our investigation on the practical scenario of embedded bio-signal analysis, a domain in which energy efficiency is key, while applications are inherently error-tolerant to a certain degree. Targeting a domain-specific multi-core platform, we present a study of the impact of inexactness on application-visible errors. en, we introduce a novel methodology to manage them, which requires minimal hardware resources and a negligible energy overhead. Experimental evidence show that, by tolerating 900 errors/hour, the resulting inexact platform can achieve an efficiency increase of up to 24%, with a QoS degradation of less than 3%

i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-signal Processing

Smart edge sensors for bio-signal monitoring must support complex signal processing routines within an extremely small energy envelope. Coarse-Grained Reconfigurable Arrays (CGRAs) are good candidates for tackling these conflicting objectives because, thanks to their flexibility and high computational density, they can efficiently support the computational hot-spots characterizing bio-DSP applications. The Interleaved- Datapaths (i-DPs) CGRA presented in this paper further leverages the benefits of this architectural paradigm, focusing on ultralow energy operation. Its defining feature is the complex design of its computing cells, which, by embedding multiple i-DPs, allow a high ratio between computing and control logic, effectively speeding up computations, and resulting in a marginal impact on the required IC area. Interleaved datapaths increase the energy efficiency of up to 33 %, with respect to a single-DP alternative, when executing common kernels in the multi-lead ECG signal processing field

Heterogeneous error-resilient scheme for spectral analysis in ultra-low power wearable electrocardiogram devices

Wearable devices performing advanced bio-signal analysis algorithms will foster a revolution in healthcare provision of chronic cardiac diseases. In this context, energy efficiency is of paramount importance, as long-term operations must be performed within an extremely tight power budget. Aggressive voltage scaling is an effective strategy towards this goal, but presents the adverse effect of causing bit-flip errors in the memory sub-system. The application of error correction codes to the whole memory results in large area and energy overheads. To cope with this challenge, in this paper we propose to selectively protect only data presenting high significance, i.e.: highly impacting the end-to-end quality of service. The resulting heterogeneous error protection scheme allows substantial energy savings with respect to complete protection, while resulting in negligible results degradation of cardiac bio-signal processing algorith